Phase-locked loops (PLLs) are feedback control systems that are often an essential part of many telecommunications devices. PLLs are used in modulators and demodulators, in frequency synthesizers, in clock synchronizations circuits and in many other high-speed communication applications. PLL can be implemented using digital or analog devices.
FIG. 1A shows a block diagram of a prior art PLL. The PLL shown in FIG. 1 includes four main components, namely, a Phase Frequency Detector (PFD) 11, a Filter 12, a Variable Frequency Oscillator (VFO) 13 and feedback loop with an adjustable frequency divider 14. The VFO 13 could for example be a Voltage Controlled Oscillator (VCO).
The PFD 11 compares the phase and frequency of the feedback signal to the reference signal and it generates an error signal indicating any difference it detects. The error signal generated by PFD 11 passes through the filter 12 and is used to adjust the frequency of the VFO 13. Any differences between the input signal and the feedback signal are thus used to change the frequency of the VFO.
A PLL can be used as a frequency multiplier. For example, in the circuit shown in FIG. 1, the output of the reference signal may be a 10 Mhz signal. The output of the VCO may for example be a 1 Ghz signal. In such a PLL the frequency divider 14 would divide the 1 Ghz output signal down to a 10 Mhz signal. The frequency divider 14 can be adjusted to a higher or lower divisor in order to change the output frequency of the PLL.
There is great deal of published literature which describes the design and operation of prior art PLLs. For example, PLL technology is described in a text book entitled “Phase-Locked Loops” by Roland Best, ISBN: 0071412018, dated Jun. 20, 2003. Other books and literature which describe the principles and applications of PLL are also available.
When the frequency of a prior art PLL is changed, some time is required for the circuit to move between frequencies. FIG. 1B illustrates that as a PLL moves from a frequency A to a frequency B, the frequency may first go to a frequency C which is highest frequency at which the circuit is capable of operating. It may lock at this frequency for some time and finally drop back down to frequency A. FIG. 1B is intended merely to show that the frequency fluctuates or varies and that it may lock at the circuit's upper (or lower) frequency for a considerable time period. In general, the locking can be caused by physical limitations of the circuit, such as, not enough frequency range or not enough voltage range of the filter. While (for convenience of illustration) only a few fluctuations (or oscillations) are shown in FIG. 1B, in general, there will be may such fluctuations. The important point that FIG. 1B illustrates is that when the frequency of the circuit is changed, a considerable time may elapse before the circuit settles down at its new frequency.
It is often desirable to have a circuit that settles quickly when the operating frequency is changed. This can be particularly important in applications such as in radio frequency (RF) circuit which do frequency hopping and which have a “tight” frequency range. In such circuits it is important that the circuit settle at a new frequency quickly. Furthermore, such circuits may have a tendency to clamp at the extreme upper and lower frequency limits for a considerable period of time (relative to the frequency period), when the frequency of the circuit is adjusted.
Several different techniques are known to shorten the time required for a PLL to settle at a new frequency. One such prior art technique uses a VCO that has a wider frequency range than what is actually needed. In order to have a wide frequency range, the VCO must have a large VCO gain Kv (MHz/V). In general, VCOs with large Kv are undesirable because they will consume more power, be susceptible to noise at the input to the VCO, and will also exhibit different behavior (e.g., lock times and PLL bandwidth) than the VCO with a small Kv.
Another prior art technique uses a dual-gain scheme of coarse and fine gain control for the VCO. The disadvantage to this technique is that it greatly increases the complexity of the VCO design, complicates the overall system design (when to switch between coarse and fine gain, how to handle the coarse to fine transition, etc.), requires additional devices and therefore a larger layout, and also requires high power since the counters must be able to keep up with the VCO frequency.
A third prior art technique is to adjust the PLL to have a large forward gain. This may be accomplished by adjusting the VCO gain, the pump current, or filter parameters. This technique also complicates the PLL design and requires high power for the counters to keep up with the VCO frequency. Additionally, in the problem area where the VCO is clamped, adjusting the PLL parameters is useless. Furthermore, speeding up the lock response may cause even more overshoot into the clamped region of the VCO, which actually hurts lock time.
The present invention provides an improved technique for decreasing the amount of time required for a PLL to settle at a new frequency when the frequency of the PLL is changed.